Cadence announced that WillSemi's Cadence Virtuoso custom IC design platform enhances analog IC design excellence and reduces overall product time to market. Compared to previously deployed industry solutions, WillSemi's Cadence custom integrated circuit design process not only cuts analog design and implementation time in half, but also reduces overall design cycle time by a third.
The Cadence Custom Design Process tool helps the WillSemi IC design team achieve the following goals:
Reduce total turnaround time by 30-50% using the Virtuoso Schematic Editor with the Virtuoso Layout Suite: The Virtuoso Schematic Editor comes with a wide variety of built-in, well-defined component libraries for various emulations to speed up analog circuit design times. At the same time, its convenient wiring function greatly reduces the circuit schematic creation time and reduces the occurrence of errors. Using the Virtuoso layout Suite, WillSemi's team is able to improve the efficiency and accuracy of layout design using a method based on circuit schematic constraints.
What are the advantages of WillSemi's Cadence Virtuoso custom IC design platform?
Virtuoso simulation design environment is adopted to improve design robustness: it can detect circuit design problems, speed up debugging process and optimize design efficiency while making it easier to get started.
Increase simulation throughput and productivity with Spectre Circuit Simulation Platform: With Spectre circuit simulation platform, WillSemi maintains design integrity throughout the design cycle, increasing simulation throughput and improving productivity.
"Our previous design process used multiple products from different EDA suppliers, which was difficult to run in a coordinated way," said Ji Gang, vice president of research and development at WillSemi. "Cadence Virtuoso's custom IC design platform is streamlined and helps us solve some of the most challenging design, validation, and implementation challenges we face to bring our products to market, thanks to the ease of use of Cadence's design process and the incredible support Cadence provides us."
After that, I went back to school to "recharge". Besides preparing for exams, I spent time in the library. The next semester of the third year bought a set of Taiwan a company 16 microcontroller development board, at that time the microcontroller just came out of time is not long, but the publicity is very exaggerated, by a university plan and the lowest price on campus wind roll up.
From the market to buy a companion textbook, because it is a edition, except for the introduction of the basic one or two pages can see errors. Because PLCC package was mainly promoted at that time, the pin number and pin number on the corresponding chip data manual of the same type of patch package were not consistent with the chip number...... Later to the outside company to do a project, "dare" to use this single chip microcomputer, surprised to find that this single chip microcomputer is still some temper, run to stop, stop when the internal is no longer a bit, it seems that the internal clock part is unstable... Later simply did not use this single chip microcomputer. Now think about it, in fact, the phenomenon of chip stop vibration is quite common, the crystal failure rate and the chip internal clock failure probability is relatively high.
I made two more on and off during my senior year, and then bought an ARM7 board (S3C4510). When buying did not care too much about the information, see the above resources are very much, the function is strong...... Later in the process of using a lot of problems, only to find that they provided the schematic diagram is rigged, with the board does not match. Moreover, since the board only carries one page of data and cannot directly use ADS(in order to prevent plagiarism, the FLASH data cable has been changed, and the command to start FLASH write operation has also changed), it takes too much time to learn, so up to now, this board has only been my "collection". Later, I found Jie Pai. I kept trying to improve my own board, making samples again and again and changing the design draft. I played once in three days and 4 times in half a month. Later, I could not help feeling "this is what the development board should have looked like".
Many of my classmates started to look for jobs in November, while I still focused on my studies. Even if I occasionally went to a job fair with my classmates, I could not send one or two resumes. On the one hand, my English is not good enough to meet the psychological needs of most enterprises... On the other hand, I think the senior year is a good opportunity to learn -- freshman, sophomore, junior almost finished all the * classes, the senior basically no classes, if you can use this year to learn the first three years of things a good system integration, there should be a great improvement.