High-speed backplane designers face several major challenges, including signal attenuation, inter-symbol interference (ISI), and crosstalk. Chip products with innovative signal-tuning technologies, such as high-speed backplane interface solutions, can effectively solve these system-level challenges, enabling system vendors to deliver high-performance and scalable systems to their customers, while reducing development time and costs.
In modular chassis based systems such as routers, Ethernet switches, and storage subsystems, high-speed backplanes require high levels of signal integrity and higher system throughput. System vendors for these applications are facing a number of challenges to design these high-speed backplanes in an economical and timely manner. They must also protect their customers' investments in existing cable cards, chassis, and power supplies, while also supporting higher performance and offering newer services.
Today, backplanes in some systems are running on 5Gbps or faster serial link technology. To design highly reliable systems that can operate at this rate, chip manufacturers are required to provide solutions that ensure error-free transmission in the backplane. This paper describes high-speed backplanes in modular chassis based systems and their design challenges, and discusses chip solutions that address these challenges.
Example of system based on modular chassis
Modular chassis systems like core routers, enterprise switches, and storage subsystems all have high-speed backplanes and multiple wire cards. System performance and capacity can be improved by adding more cards and increasing the density of card ports. These systems are modular and can be independently extended. They are also designed to be highly available to ensure continuous operation.
These systems consist of slots containing redundant switch cards, cable cards, and power modules. They can be equipped with redundant components to increase installation reliability and availability. Figure 1 shows a typical system configuration based on a modular chassis. The backplane interface solution (also known as High speed Serial Connection) provides full duplex communication between high speed backplanes. The speed of serial connected devices depends on the system throughput requirements. Serial connections transmit data via high-speed differential signals. This differential signal is then routed through wire cards and connectors, through the backplane and through another set of high-density connectors. The channel characteristics depend on backplane material, connector density, line width/coupling, etc. In a typical router, the cable length can range from 1 "to 48" depending on where the card is inserted into these cables.
The backplane interface devices in these modular chassis systems have the following key requirements:
1. Increase speed: Interface components should be able to meet the increasing bandwidth requirements of the system designer. Chipmakers are currently selling 3.125-5Gbps rates and are offering prototypes of 6.25Gbps solutions to upgrade existing solutions in backplanes. Through the simple switch card upgrade, system manufacturers can reuse the existing chassis and line cards, and provide a way to upgrade to higher bandwidth line cards, to provide customers with more services at a low cost;
2. Backward compatibility: The backplane interface device is required to operate at the speed of the original cable card in order to be compatible with the original cable card.
3. High density and low power consumption: To cope with increasing network traffic, these systems require smaller space occupancy and higher performance and density without additional power consumption. Therefore, there is always a need for lower power consumption and faster backplane devices.
4. Manufacturability and testability: Backplane interface devices need to integrate functions such as JTAG and BIST to enable chip-level and system-level testing during prototyping and manufacturing.
High speed backplane design considerations
As data rates rise beyond the 1Gbps level, designers must solve new problems in their backplane system design. The signal integrity of these backplanes is affected by factors such as skin effect, dielectric loss, greater noise due to cross talk, and inter-symbol interference (ISI).
The skin effect is the phenomenon that as the frequency increases, most of the current will be concentrated on the outer conductor. The loss caused by the skin effect is proportional to the square root of the frequency, the width and height of the line.
Dielectric loss is caused by heat loss of plate dielectric and increases linearly with frequency. At higher frequencies, dielectric loss becomes a more serious problem. These losses not only reduce the amplitude of the signal but also slow down the edge speed of the signal, thus resulting in poor signal divergence and buffeting tolerance.
Because the less attenuated low frequency component is added to the more attenuated high frequency component at the receiver, the divergence of the signal will result in intersymbol interference. As a result, the eye pattern opening becomes smaller and therefore more difficult to recover at the receiver, resulting in unacceptable bit error rates. This limits the maximum bit rate. Another way to explain the phenomenon is that the signal "gets dirty" or diverges, causing the energy to drop bit by bit, which in turn generates bit error. At lower rates, ISI can be corrected because there is sufficient timing margin. But at higher rates, ISI is no longer limited to the signal boundary, but can affect the whole bit width.
The main source of noise is crosstalk caused by high density connectors and backplane wiring. Crosstalk is a major noise source caused by high density connector and backplane layout wiring. There are two types of crosstalk: proximal crosstalk (NEXT) and remote crosstalk (FEXT). NEXT is caused when a signal from a transmitter close to the victim receiver interferes with the received signal. FEXT occurs when the received signal is interfered by a "remote transmitter" connected to the victim receiver. All of this channel damage can be compensated or eliminated with special signal adjustment (e.g. pre-weighting and equalizing) circuits in backplane interconnect devices. These circuits compensate for signal loss by attenuating low frequency components and amplifying high frequency components.
Innovative signal adjustment technology
The key role of backplane interface devices is to solve the channel damage problems such as loss and crosstalk and thus extend the service life of backplane. The interface transmitter has amplitude control and pre-weight signal adjustment circuit.
Similarly, the backplane interface receiver uses equalization technology to control losses. In addition, these devices are required to have testable features such as JTAG and BIST for system-level testing at the time of manufacture. National Semiconductor's four-way 5Gbps SerDes meet all of these requirements. The following describes in detail the signal integrity technology used by the four-way 5Gbps backplane transceiver SCAN50C400 pair and other high-speed backplane interface devices.